1) Field of the Invention
The present invention relates to a multi-access method for a storage level including a plurality of pairs, each composed of a data array and a tag array, in an information processing apparatus including a plurality of storage levels, and further to a technique applied to a cache memory device which is interposed between a processor and a storage device so as to speed up a data read in the information processing apparatus. Particularly, the invention relates to a multi-access method and a multi-access cache memory device which enable multi-access.
2) Description of the Related Art
Conventionally, a large quantity of hardware is required for concurrently performing a plurality of accesses (multi-access) to a set associative type cache memory.
For example, according to a technique disclosed in Japanese Patent Application Laid-Open (kokai) No. 64-23354, a plurality of cache memories (buffer memory devices) are provided. When a write request is issued with respect to data shared by cache memories, a write is performed for all cache memories which share the data. In addition to this technique, various other protocols are known. These techniques require a plurality of cache memories themselves, resulting in a quite large quantity of hardware.
According to a technique disclosed in Japanese Patent Application Laid-Open (kokai) No. 1-280860, a multi-port memory is used as a cache memory so as to enable multi-access. However, this technique requires a larger number of gates, resulting in a quite large quantity of hardware. Also, this technique has a problem that this type of memory is not suited for high-speed operation.
Japanese Patent Application Laid-Open (kokai) No. 4-199242 discloses a cache memory device in which only the address array of each way has a multi-structure. As shown in FIGS. 30(a) and 30(b), this cache memory device includes two address arrays (tag arrays) 100A and 100B. The content of the address array 100A is a duplicate of that of the address array 100B. That is, the address arrays 100A and 100B have the same content.
FIGS. 30(a) and 30(b) show a 4-way set associative type cache memory device in which each of the address arrays 100A and 100B is divided into four according to the number of ways. As shown in FIG. 31, the data array 102 is also divided such that a read/write is enabled way by way. These divided data arrays 102 are shared by the two address arrays 100A and 100B.
In the above-described cache memory device, when two accesses A and B are received concurrently as a first step as shown in FIGS. 30(a) and 30(b), each of the address arrays 100A and 100B is searched through using as an index a part of an actual address assigned to each of the accesses A and B. When the search provides a result, the result (actual address) of the search is compared with an actual address received in conjunction with each of the accesses A and B by comparators 101A and 101B, respectively, thereby determining a level (memory hierarchy, way) where data required by each of the accesses A and B is present.
When levels (ways) obtained through comparison by the comparators 101A and 101B are not the same, as a second step, multiple accesses are performed to data (DATA1, DATA3) which are present in data arrays 102 of different levels (ways) as shown in FIG. 31.
However, even in this cache memory device, the quantity of hardware becomes larger due to employing the multi-structure of the address arrays 100A and 100B. Also, an access cannot be performed to a data array before a level (way) is determined. That is, an access to the address arrays 100A and 100B and an access to the data array 102 (see FIG. 31) cannot be performed concurrently, resulting in a failure to significantly speed up multi-access processing.
As described above, the conventional methods for multi-access to a cache memory cause an increase in quantity of hardware and fail to significantly speed up multi-access processing.